The diode with high voltage at the anode terminal will get ON first. So, D₃ will become ON which will result in D₁ and D₂ be OFF.

Therefore, $I=\frac{5-1}{1k\mathrm{\Omega }}=4mA$

Note: Two parallel devices (diodes, thyristors, BJT, etc.) cannot be ON at the same time. In a parallel connection, only one device shall operate.

Each of the given options corresponds to a clamper.

1. It is a negative clamper whole signal will be clamped down. The reference voltage is +2V therefore the whole signal will be below +2V.

2. It is a negative clamper with reference voltage -2V. Therefore, here the entire signal will clamp down below -2V.

3. It is a positive clamper (diode pointing upward) and the reference voltage is 2V. Therefore entire signal will clamp up above 2V.

4. It is a positive clamper with reference voltage -2V. Therefore, the entire signal will clamp up above -2V.

During the positive cycle, the first diode conducts and charges the first capacitor to a voltage V_m.

When the negative cycle arrives, the second diode starts to conduct which then charges the second diode to the peak negative input voltage. This results in a total output voltage of 2V_m, where V_m is the peak input voltage.

In other words, the circuit given in question represents a voltage doubler circuit. therefore, double the input voltage appears across the output.

• The input signal to the differentiator circuit is applied to the capacitor. The capacitor blocks any DC content so there is no current flow to the amplifier summing point.
• The capacitor only allows AC type input voltage changes to pass through and whose frequency is dependent on the rate of change of the input signal.
• Therefore, the output voltage V_out is a constant –R_ƒC times the derivative of the input voltage V_in with respect to time. The minus sign (–) indicates a 180^o phase shift because the input signal is connected to the inverting input terminal of the operational amplifier.

${\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}=-\mathrm{R}\mathrm{C}\frac{\mathrm{d}{\mathrm{V}}_{\mathrm{i}\mathrm{n}}}{\mathrm{d}\mathrm{t}}$

The output waveform is,

If the time constant or time response is faster than the output waveform will appear as a spike, as shown in option D.

Operational Amplifier as Differentiator:

${\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}=-\mathrm{R}\mathrm{C}\frac{\mathrm{d}{\mathrm{V}}_{\mathrm{i}\mathrm{n}}}{\mathrm{d}\mathrm{t}}$

The differentiator performs mathematical differentiation operation on the input signal with respect to time, i.e. the output voltage is proportional to the rate of change of the input signal.

Differentiating circuits are commonly used to operate on triangular and rectangular signals. While operating on sine wave inputs, differentiating circuits have frequency limitations.

Operational Amplifier as Integrator:

${\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}=-\frac{1}{\mathrm{R}\mathrm{C}}{\int }_0^{\mathrm{t}}{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\mathrm{d}\mathrm{t}$

• An integrating circuit performs the mathematical operation of integration with respect to time, on the input signal, i.e. the output voltage is proportional to the applied input voltage integrated over time.
• The output of an integrator is out of phase by 180^o with respect to the input since the input is applied to the inverting input terminal of the op-amp.
• Integrating circuits are generally used to generate ramp wave from square wave input. Integrating amplifiers have frequency limitations while operating on sine wave signals.

By voltage division,

$V_a=V_i\left(\frac{2}{1+2}\right)=\frac{2}{3}{V}_i$ 

From virtual ground concept, $V_a=V_b=\frac{2}{3}{V}_i$ 

By applying KCL at V_b

$\frac{V_b}{3}+\frac{V_b-V_0}{R_f}=0$ 

$\Rightarrow \frac{V_0-V_b}{R_f}=\frac{V_b}{3}$ 

$\Rightarrow V_0-\frac{2}{3}{V}_i=R_f\left(\frac{2}{9}{V}_i\right)$ 

$\Rightarrow V_i\left(\frac{V_0}{V_i}-\frac{2}{3}\right)=R_f\left(\frac{2}{9}{V}_i\right)$ 

$\Rightarrow R_f\left(\frac{2}{9}\right)=\left(\frac{V_0}{V_i}-\frac{2}{3}\right)$ 

Given that, voltage gain $\frac{V_0}{V_i}=5$ 

$\Rightarrow R_f\left(\frac{2}{9}\right)=\left(5-\frac{2}{3}\right)$ 

$\Rightarrow R_f=\frac{13}{3}\times \frac{9}{2}=19.5k\mathrm{\Omega }$ 

Concept:

1) Sampler

a)Voltage sampler: If the feedback signal is taken from collector(or drain), then it is a voltage sampler

b)Current sampler: If the feedback signal is taken from emitter (or source), then it is a current sampler.

2)Mixer

a)Series mixer: If the feedback signal is added just before the biasing component, it is called series mixer.

b)Shunt mixer: If the signal is directly added to the base (or gate), it is a shunt mixer.

Type of feedback:

• In the output side, current is getting sampled; therefore it is current sampling. For current sampling, the connection is series.
• At the input, the feedback signal gets directly connected to input terminal. The input current is getting mixed with part of output current. Hence it is a current mixer. Current-current mixer is a shunt mixer.

Feedback type → Shunt (input) – Series feedback (output)

Feedback factor (β):

For calculation of feedback factor, break the series side and ground the shunt side.

Here input → (source) → shunt

Output → series

ground the source (input) and break the output node.

$I_f=I_0\frac{1k\mathrm{\Omega }}{1k\mathrm{\Omega }+2k\mathrm{\Omega }}$

$I_f=I_0\left(\frac{1}{3}\right)$

$\beta =\frac{I_f}{I_0}=\frac{1}{3}$

Hysteresis voltage V_H= V_UTP - V_LTP

V_H = 3 - (-2) = 5 V

A clockwise circulating noise eliminating loop corresponds to an inverted Schmitt trigger while an anti-clockwise loop corresponds to a non-inverting Schmitt trigger. 

To check if the Zener diode is ON or OFF, we evaluate the voltage across the Zener by assuming it to be OFF, i.e.

$V_A=\frac{10\times 1k}{1k+5.6k}$ (Voltage-Division)

V_A = 1.515 V

Since, V_A < V_z, the Zener diode is in the OFF state, i.e. Zener diode will not be operating in the breakdown and I_Z = 0 A

The given circuit is an RC phase shift oscillator.

$I_3=\frac{V_2}{R}$

$V_4=V_2+\frac{I_3}{j\omega C}$

$V_4=V_2+\frac{V_2}{j\omega CR}$        ---(1)Similarly

$I_2=I_3+\frac{V_4}{R}$

Replacing the value of V₄ we get $I_2=\frac{V_2}{R}+\frac{1}{R}\left[V_2+\frac{V_2}{j\omega CR}\right]$       ---(2)

$V_3=\frac{I_2}{j\omega C}+V_4$      ---(3)

Replacing value of, I₂, V₄ in (3) we get

$V_3=\frac{V_2}{j\omega CR}+\frac{V_2}{j\omega CR}+\frac{V_2}{{\left(j\omega CR\right)}^2}+V_2+\frac{V_2}{j\omega CR}$

$I_1=I_2+\frac{V_3}{R}$

Replacing values of I₂ & V₃ in terms of V₂

$I_1=\frac{2V_2}{R}+\frac{4V_2}{j\omega C{R}^2}+\frac{V_2}{R{\left(j\omega CR\right)}^2}+\frac{V_2}{R}$

$V_1=\frac{I_1}{j\omega C}+V_3$

Replacing I₁

$V_1=V_2\left[\left[1-\frac{5}{{\omega }^2{C}^2{R}^2}\right]+j\left[\frac{1}{{\omega }^3{C}^3{R}^3}-\frac{6}{\omega CR}\right]\right]$

For frequency of oscillation is,

$I_m\left(V_1\right)=0\Rightarrow \frac{1}{{\omega }^3{C}^3{R}^3}=\frac{6}{\omega CR}$

${\omega }^2=\frac{1}{6R^2{C}^2}$

$\omega =\frac{1}{\sqrt{6}RC}$

$f=\frac{\omega }{2\pi }$

$f=\frac{1}{2\pi RC\sqrt{6}}=\frac{1}{2\pi \times 10\times 10\times {10}^{-6}\times \sqrt{6}}$

f = 649.74 Hz

Concept:

The maximum rate of change of the output voltage in response to a step input voltage is defined as the slew rate of the op-Amp.

Mathematically, the slew rate is defined as:

$S.R={\left(\frac{d{V}_0}{dt}\right)}_{max}$

Application:

For the given waveform, the time between the upper limit to the lower limit of the output is 1 μs.

For the given waveform, the slew rate will be obtained as:

$S.R.={\left(\frac{\mathrm{\Delta }{V}_0}{\mathrm{\Delta }t}\right)}_{max}$

$S.R=\frac{9-\left(-9\right)}{1\mu S}$

Concept:

The Voltage gain for an Emitter Bias Configuration in given by:-

$\Rightarrow A_v=\frac{-\beta R_c}{\left(\beta \right)(R_E+r_e)}\approx \frac{-\beta R_c}{\beta \left(R_E\right)}=-\frac{R_c}{R_E}$

Calculation:

Given, R_c = 2.2 K.

R_E= 0.5 kΩ

We known that

$\frac{g_m}{C}=Av\times B.W$

$\frac{190\times {10}^{-3}}{1000\times {10}^{-12}}=60\times B.W$

B.W = 3.167 MHz

Zener diode acts as a voltage regulator when it is reverse biased.

When Zener diode is in ON state, the voltage across it will remain V_z = 20 V and I_zmax = 60 mA

$\therefore V_{R_L}=20V$

$I_{R_L}=\frac{V_{R_L}}{R_L}=\frac{20V}{1.2k\mathrm{\Omega }}=16.67mA$

I_max = 16.67 mA + 60 mA

I_max = 76.67 mA

$V_{imax}=I_{max}R+V_z$

$V_{imax}=\left(\frac{76.67}{1000}\right)\left(220\right)+20$

V_{i max} = 36.87 V

During the positive input cycle:

D₁ → RB (OFF); D₂ → FB (ON)

Circuit becomes,

At the V_in reaches 4V; D₂ becomes ON

V_in > 4 V, V₀ = 4 V

0 < V_in < 4 V, D₂ = OFF; D₁ = OFF , V₀ = V_in

During negative half cycle:

D₁ = ON, D₂ = OFF

V_in < -4 V, $V_0=\left(\frac{V_{in}+4}{20k}\right)10k-4V$

-4V < V_in < 0 , V₀ = V_in (D₂ = OFF, D₁ = OFF)

After circuit analysis, the output waveform is as given below.

${\left(V_0\right)}_{min}=\left(\frac{{\left(V_{in}\right)}_{max}+4}{20k}\right)10k-4=-7V$

V_{o min} + V_{o max} = 4 - 7 = -3 V

Given that,

V_in = 2 cos (100t) V

${\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}=2\cos \left(100\mathrm{t}-\frac{\pi }{2}\right)\mathrm{V}.$

R = 1 kΩ = 1000 Ω

Apply superposition at point A,

V_in at non-inverted (+) terminal and inverted (-) terminal at the ground.

${\mathrm{V}}_1={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\frac{\left(-\frac{\mathrm{j}}{\omega \mathrm{C}}\right)}{\left(\mathrm{R}-\frac{\mathrm{j}}{\omega \mathrm{C}}\right)}\times \left(1+\frac{\mathrm{R}}{\mathrm{R}}\right)$

Now V_in at inverted (-) terminal and non-inverted (+) terminal at the ground.

${\mathrm{V}}_2=-V_{in}\left(\frac{\mathrm{R}}{\mathrm{R}}\right)$

So that the output voltage is,

V_out = V₁ + V₂

${\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\frac{\left(-\frac{\mathrm{j}}{\omega \mathrm{C}}\right)}{\left(\mathrm{R}-\frac{\mathrm{j}}{\omega \mathrm{C}}\right)}\times \left(1+\frac{\mathrm{R}}{\mathrm{R}}\right)-{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\frac{\mathrm{R}}{\mathrm{R}}\right)$

${\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}=\frac{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}}{1+\mathrm{j}\omega \mathrm{R}\mathrm{C}}$ $\times \left(1+\frac{1}{1}\right)-{\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\frac{1}{1}\right)$

${\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}=\frac{2\times {\mathrm{V}}_{\mathrm{i}\mathrm{n}}}{1+\mathrm{j}\omega \mathrm{R}\mathrm{C}}-{\mathrm{V}}_{\mathrm{i}\mathrm{n}}$  

${\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\frac{2-1-\mathrm{j}\omega \mathrm{R}\mathrm{C}}{1+\mathrm{j}\omega \mathrm{R}\mathrm{C}}\right)$

${\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}\left(\frac{1-\mathrm{j}\omega \mathrm{R}\mathrm{C}}{1+\mathrm{j}\omega \mathrm{R}\mathrm{C}}\right)$

V_in = 2 cos(100t) and ω = 100rad.

$\therefore {\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}=2\cos (100\mathrm{t}-2{\tan }^{-1}\left(\omega \mathrm{R}\mathrm{C}\right))$

$\therefore 2{\tan }^{-1}\left(\omega \mathrm{R}\mathrm{C}\right)=\frac{\pi }{2}$

$\omega \mathrm{R}\mathrm{C}=\mathrm{t}\mathrm{a}\mathrm{n}\frac{\pi }{4}$

⇒ 100 × 1000 × C = 1

⇒ C = 10 μF

By using virtual ground concept,

V_a = V_b = 0 V

By applying KCL at V_a,

$\frac{V_a-V_1}{R_1}+\frac{V_a-V_2}{R_2}+\frac{V_a-V_{out}}{\frac{1}{j\omega C}}=0$ 

$\Rightarrow V_{out}=\frac{-V_2}{j\omega C{R}_2}-\frac{V_1}{j\omega C{R}_1}$ 

V₁ = 10 sin 200 t = 10 cos (200 t – 90°)

= 10 ∠-90° = -10j

V₂ = 15 sin 200 t = -15 j

$V_{out}=\frac{-j15}{j\left(200\right)\left(2\times {10}^{-6}\right)\left(0.5\times {10}^6\right)}-\frac{-j10}{j\left(200\right)\left(2\times {10}^{-6}\right)\left(0.75\times {10}^6\right)}$ 

$=\frac{15}{200}+\frac{10}{300}=0.1083$ 

V_out = 0.1083 cos (200 t) 

• The first two op-amps have their inverting inputs at a virtual ground due to the connection to ground at their noninverting inputs.
• The two 40 kΩ resistor do not induce any voltage drop between the first pair of op-amps, as the currents into the op amp inputs are always 0.
• Because both of the middle op amps are buffers, V_x and V_y get carried over to their outputs.
• There is no voltage drop across the bottom 0.5 kΩ resistor due to lock of current.

Both V_x and V_y are given by inverting amplifiers:

$V_x=-\frac{8k}{2k}{V}_1=-4V_1$ 

$V_y=-\frac{16k}{2k}{V}_1=-8V_2$ 

KCL at the inverting input of the last op-amp given us

$\frac{V_y-V_x}{0.5k}+\frac{V_y-V_0}{4k}=0$ 

⇒ V₀ = 32 V₁ – 72 V₂

Concept:

For a 555 timer, the given pin connection represents an astable 555 timer.

The charging time is given by the formula.

⇒ T_c = 0.693 (R₁ + R₂) C

Discharging time ⇒ T_d = 0.693 R₂ C

Total time ⇒ T = T_c + T_α = 0.693 (R₁ + 2R₂)C

Calculation:

For the given question

R₁ = 2.2 kΩ; R₂ = 4.7 kΩ; C = 0.22 μF

T = 0.93 (R₁ + 2R₂)C

T = 0.693 (2.2 + (2 × 4.7)) × 10³ × 0.22 × 10^-6

Frequency of oscillation is

$f=\frac{1}{T}=\frac{1}{0.693\times 0.22\times 11.6\times {10}^{-3}}$

f = 0.565 kHz  

Concept:

Inverting closed-loop positive feedback Schmitt trigger is shown below.

$V_{UTP}=V_{R_1}=V_{sat}\frac{R_1}{R_1+R_2}$

$V_{LTP}=V_{R_2}=-V_{sat}\frac{R_1}{R_1+R_2}$

For V_i < V_UTP     V₀ = +V_sat

V_i > V_UTP        V₀ = -V_sat

Hysteresis width V_H = V_UTP - V_LTP

Calculation:

V_x is the actual inverting input to the op-Amp.

At node X:

$\frac{V_x-V_{in}}{10k}=\frac{2-V_x}{20k}$

$V_x=\frac{2+2V_{in}}{3}$

$V_{uT{P}_1}=V_{R_1}=V_{sat}\frac{R_1}{R_1+R_2}=10\left(\frac{5k}{5k+20k}\right)=2V$

For $V_x>V_{uT{P}_1}$ V₀ = -V_sat

$\frac{2+3V_{in}}{3}>2$

i.e. $V_{in}>\frac{6-2}{2}=2V$

For V_x > -2V       V₀ = +V_sat

$\frac{2+2V_{in}}{3}>-2$

$V_{LTP}=V_{in}>\frac{-6-2}{2}=-4V$

V_H = V_uTP - V_LTP = 2 – (-4) = 6 V

From the given dc load line, we have:

V_CEQ = 6 V

I_CQ = 48 mA

Since, I_E = I_C + I_B

Since I_C = β I_B, the emitter current can be written as:

$I_E=I_C+\frac{I_C}{\beta }$

$I_E=I_C\left(\frac{\beta +1}{\beta }\right)$

For the given I_CQ and β, I_EQ will be:

$I_{EQ}=4.8m\left(\frac{120+1}{220}\right)$

I_EQ = 4.84 mA

∴ The circuit is redrawn as:

Applying KVL for the above loop, we get:

18 - I_CQ R_C - V_CEQ - I_EQ R_E = 0

18 – 4.8 m × 2x – 6 – 4.84 m × R_E = 0

$R_E=\frac{18-9.6-6}{4.84m}$

R_E = 0.496 kΩ

Concept:

The BJT configuration for a pnp and npn transistors are as shown:

The emitter-collector voltage can be calculated using KVL

Analysis:

The configuration given is of a PNP transistor.

Given, V_E = 3 V

V_EB = 600 × 10^-3 V = 0.6 V

V_E – V_B ⇒ 0.6 V

3 – V_B ⇒ 0.6 V

So, V_B = 2.4 Volts

Applying Ohm’s law across 60 kΩ resistor,

$I_B=\frac{V_B}{60\times {10}^3}=\frac{2.4}{60\times {10}^3}$

$I_B=0.04\times {10}^{-3}A$

I_C = β I_B (where β is the current gain)

Given, β = 50,

I_C = 50 × 0.04 × 10^-3 A = 2 mA

I_C = 2 × 10^-3 A

Applying Ohms law across 500 Ω resistor, we get:

$I_C=\frac{V_C}{500}=\frac{V_C}{500}$

$I_C=2\times {10}^{-3}$

$V_C=1Volts$

Now,

V_EC = V_E­ – V_C = 3 – 1 = 2 Volts

So, V_EC = 2 Volts

Common Mistakes:

β = 200, α = 0.995

Collector (I_c) = α I_E = 0.995 × 10 = 9.95 mA

V_c = 9.95 × 100 = 0.995 V

Base current $I_R=\frac{10}{200}=0.05mA$

V_B = 1.5 – 10 k × 0.05 = 1 V

V_BC = 0.005

For an n-channel enhancement mode MOSFET, transition point is given by:

V_DS(sat) = V_GS - V_th

= V_GS – 2

From the circuit,

V_DS = V_GS

⇒ V_Ds(sat) = V_DS – 2

⇒ V_DS = V_DS(sat) + 2

⇒ V_­DS > V_DS(sat)

So, the transistor will always be in the Saturation region.

I_D = K (V_GS - V_th)²

⇒ 4 = K (V_GS - 2)²

V_GS = V_DS = 10 – I_D R_­D = 10 – 4(1) = 6 V

⇒ 4 = K (6 -2)²

⇒ K = 0.25

Now R_D is increased to 4 kΩ, Let current $I{}^{\prime }{}_d$ and voltages are $V{}^{\prime }{}_{DS}=V{}^{\prime }{}_{GS}$

Applying current equation

$I_D^{\prime }=K{\left(V_{GS}^{\prime }-V_{TH}\right)}^2$

$I_D^{\prime }=\frac{1}{4}{\left(V_{GS}^{\prime }-2\right)}^2$

$V_{GS}^{\prime }=V_{DS}^{\prime }=10-I_D^{\prime }{R}_D^{\prime }=10-4I_D^{\prime }$

$4I_{DS}^{\prime }={\left(10-4I_D^{\prime }-2\right)}^2={\left(8-4I_D^{\prime }\right)}^2$

$=16{\left(2-I_D^{\prime }\right)}^2$

$I_D^{\prime }=4\left(4+I_D^{\prime }-4I_D^{\prime }\right)$

$\Rightarrow 4{\left(I_D^{\prime }\right)}^2-17I_D^{\prime }+16=0$

$\Rightarrow I_D^{\prime }=2.84mAor1.4mA$

It cannot be 2.84 mA because:

For I_D = 2.84 mA, VGS will be negative.

So, I_D' = 1.4 mA

In Thevenin’s equivalent circuit

$V_{th}=20\left(\frac{50K}{50K+R}\right)$

V_GS = V_th - 6K I_D

$I_D=\frac{20-12}{3K}=2.67mA$

For PMOS CKT V_GS should be -Ve

V_GS = -2V

$\begin{array}{l}-2=20\left(\frac{50K}{R+50K}\right)-5\times 2.67\\ 11.35=20\left(\frac{50K}{50K+R}\right)\\ \frac{50K}{0.567}=50K+R\end{array}$

88.105 K = 50 K + R