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Analog Electronics Test 1
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Analog Electronics Test 1
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  • Question 1/25
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    In the figure shown below, the value of current I is _______mA. Assume all diodes are ideal.

    Solutions

    The diode with high voltage at the anode terminal will get ON first. So, D3 will become ON which will result in D1 and D2 be OFF.

    Therefore, I=511kΩ=4mA

    Note: Two parallel devices (diodes, thyristors, BJT, etc.) cannot be ON at the same time. In a parallel connection, only one device shall operate.

  • Question 2/25
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    Which of the following circuits have no negative voltage in the output waveform for the given input waveform?

    Solutions

    Each of the given options corresponds to a clamper.

    1. It is a negative clamper whole signal will be clamped down. The reference voltage is +2V therefore the whole signal will be below +2V.

    2. It is a negative clamper with reference voltage -2V. Therefore, here the entire signal will clamp down below -2V.

    3. It is a positive clamper (diode pointing upward) and the reference voltage is 2V. Therefore entire signal will clamp up above 2V.

    4. It is a positive clamper with reference voltage -2V. Therefore, the entire signal will clamp up above -2V.

  • Question 3/25
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    Consider the figure shown below, the value of voltage Vo is

    Solutions

    During the positive cycle, the first diode conducts and charges the first capacitor to a voltage Vm.

    When the negative cycle arrives, the second diode starts to conduct which then charges the second diode to the peak negative input voltage. This results in a total output voltage of 2Vm, where Vm is the peak input voltage.

    In other words, the circuit given in question represents a voltage doubler circuit. therefore, double the input voltage appears across the output.

  • Question 4/25
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    For the give input voltage, Vin = 10 sin (2πt) to the functional circuit shown below, the output signal will be

    Solutions

     

    • The input signal to the differentiator circuit is applied to the capacitor. The capacitor blocks any DC content so there is no current flow to the amplifier summing point.
    • The capacitor only allows AC type input voltage changes to pass through and whose frequency is dependent on the rate of change of the input signal.
    • Therefore, the output voltage Vout is a constant –RƒC times the derivative of the input voltage Vin with respect to time. The minus sign (–) indicates a 180o phase shift because the input signal is connected to the inverting input terminal of the operational amplifier.

    Vout=RCdVindt

    The output waveform is,

    If the time constant or time response is faster than the output waveform will appear as a spike, as shown in option D.

    Operational Amplifier as Differentiator:

    Vout=RCdVindt

    The differentiator performs mathematical differentiation operation on the input signal with respect to time, i.e. the output voltage is proportional to the rate of change of the input signal.

    Differentiating circuits are commonly used to operate on triangular and rectangular signals. While operating on sine wave inputs, differentiating circuits have frequency limitations.

    Operational Amplifier as Integrator:

    Vout=1RC0tVindt

    • An integrating circuit performs the mathematical operation of integration with respect to time, on the input signal, i.e. the output voltage is proportional to the applied input voltage integrated over time.
    • The output of an integrator is out of phase by 180o with respect to the input since the input is applied to the inverting input terminal of the op-amp.
    • Integrating circuits are generally used to generate ramp wave from square wave input. Integrating amplifiers have frequency limitations while operating on sine wave signals.
  • Question 5/25
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    For the ideal op amp shown, what should be the value of resistor Rf to obtain a gain of 5?

    Solutions

    By voltage division,

    Va=Vi(21+2)=23Vi 

    From virtual ground concept, Va=Vb=23Vi 

    By applying KCL at Vb

    Vb3+VbV0Rf=0 

    V0VbRf=Vb3 

    V023Vi=Rf(29Vi) 

    Vi(V0Vi23)=Rf(29Vi) 

    Rf(29)=(V0Vi23) 

    Given that, voltage gain V0Vi=5 

    Rf(29)=(523) 

    Rf=133×92=19.5kΩ 

  • Question 6/25
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    Identify the feedback type and find the feedback factor β.

    Solutions

    Concept:

    1) Sampler

    a)Voltage sampler: If the feedback signal is taken from collector(or drain), then it is a voltage sampler

    b)Current sampler: If the feedback signal is taken from emitter (or source), then it is a current sampler.

    2)Mixer

    a)Series mixer: If the feedback signal is added just before the biasing component, it is called series mixer.

    b)Shunt mixer: If the signal is directly added to the base (or gate), it is a shunt mixer.

    Type of feedback:

    • In the output side, current is getting sampled; therefore it is current sampling. For current sampling, the connection is series.
    • At the input, the feedback signal gets directly connected to input terminal. The input current is getting mixed with part of output current. Hence it is a current mixer. Current-current mixer is a shunt mixer.

     

    Feedback type → Shunt (input) – Series feedback (output)

    Feedback factor (β):

    For calculation of feedback factor, break the series side and ground the shunt side.

    Here input → (source) → shunt

    Output → series

     

    ground the source (input) and break the output node.

    If=I01kΩ1kΩ+2kΩ

    If=I0(13)

    β=IfI0=13

  • Question 7/25
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    The transfer characteristics of a Schmitt trigger is shown below:

    A. Hysteresis voltage in the circuit is 1 V.

    B. Hysteresis voltage in the circuit is 5 V.

    C. It is a non- inverting Schmitt trigger.

    D. It is an inverting Schmitt trigger.

    Choose the correct option from the options given below:

    Solutions

    Hysteresis voltage VH= VUTP - VLTP

    VH = 3 - (-2) = 5 V

    A clockwise circulating noise eliminating loop corresponds to an inverted Schmitt trigger while an anti-clockwise loop corresponds to a non-inverting Schmitt trigger. 

  • Question 8/25
    2 / -0.33

    Consider the voltage reference circuit shown in the figure. Assume op-amp is ideal. What is the value of Zener current Iz (in mA)?

    Solutions

    To check if the Zener diode is ON or OFF, we evaluate the voltage across the Zener by assuming it to be OFF, i.e.

    VA=10×1k1k+5.6k (Voltage-Division)

    VA = 1.515 V

    Since, VA < Vz, the Zener diode is in the OFF state, i.e. Zener diode will not be operating in the breakdown and IZ = 0 A

  • Question 9/25
    2 / -0.33

    For the circuit shown below the frequency of oscillation is _______ Hz

    Assume that R = 10 Ω, C = 10 μF

    Solutions

    The given circuit is an RC phase shift oscillator.

    I3=V2R

    V4=V2+I3jωC

    V4=V2+V2jωCR        ---(1)Similarly

    I2=I3+V4R

    Replacing the value of V4 we get I2=V2R+1R[V2+V2jωCR]       ---(2)

    V3=I2jωC+V4      ---(3)

    Replacing value of, I2, V4 in (3) we get

    V3=V2jωCR+V2jωCR+V2(jωCR)2+V2+V2jωCR

    I1=I2+V3R

    Replacing values of I2 & V3 in terms of V2

    I1=2V2R+4V2jωCR2+V2R(jωCR)2+V2R

    V1=I1jωC+V3

    Replacing I1

    V1=V2[[15ω2C2R2]+j[1ω3C3R36ωCR]]

    For frequency of oscillation is,

    Im(V1)=01ω3C3R3=6ωCR

    ω2=16R2C2

    ω=16RC

    f=ω2π

    f=12πRC6=12π×10×10×106×6

    f = 649.74 Hz

  • Question 10/25
    2 / -0.33

    For the step input, the output response of an op-amp is shown below. What is the value of the slew rate (in V/μS)?

    Solutions

    Concept:

    The maximum rate of change of the output voltage in response to a step input voltage is defined as the slew rate of the op-Amp.

    Mathematically, the slew rate is defined as:

    S.R=(dV0dt)max

    Application:

    For the given waveform, the time between the upper limit to the lower limit of the output is 1 μs.

    For the given waveform, the slew rate will be obtained as:

    S.R.=(ΔV0Δt)max

    S.R=9(9)1μS

    Slew Rate = 18 V/μS
  • Question 11/25
    2 / -0.33

    For the Network of the figure shown below, without CE (unbypassed), the Voltage gain Av is _____.

    Solutions

    Concept:

    The Voltage gain for an Emitter Bias Configuration in given by:-

    Av=βRc(β)(RE+re)βRcβ(RE)=RcRE

    Calculation:

    Given, R= 2.2 K.

    RE= 0.5 kΩ

    ­So, Av (Voltage Gain) = 22k0.5k=225 = - 4.4
  • Question 12/25
    2 / -0.33

    Given for a FET, gm = 190 mA/v, total capacitance = 1000 PF and voltage gain of -60. The bandwidth(in MHz) will be____
    Solutions

    We known that

    gmC=Av×B.W

    190×1031000×1012=60×B.W

    B.W = 3.167 MHz

  • Question 13/25
    2 / -0.33

    To maintain the Zener diode in ON state, the maximum value of input voltage Vi is_____ V

    R = 220 Ω

    RL = 1.2 kΩ

    Vz = 20 V

    Izmax = 60 mA

    Solutions

    Zener diode acts as a voltage regulator when it is reverse biased.

    When Zener diode is in ON state, the voltage across it will remain Vz = 20 V and Izmax = 60 mA

    VRL=20V

    IRL=VRLRL=20V1.2kΩ=16.67mA

    Imax = 16.67 mA + 60 mA

    Imax = 76.67 mA

    Vimax=ImaxR+Vz

    Vimax=(76.671000)(220)+20

    Vi max = 36.87 V

  • Question 14/25
    2 / -0.33

    A voltage signal 10 sin(ꙍt) is applied to a circuit with ideal diodes, then the sum of maximum and minimum voltages of output is__________(cut in voltage for each diode is 0.7 V)

    Solutions

    During the positive input cycle:

    D1 → RB (OFF); D2 → FB (ON)

    Circuit becomes,

    At the Vin reaches 4V; D2 becomes ON

    Vin > 4 V, V0 = 4 V

    0 < Vin < 4 V, D2 = OFF; D1 = OFF , V0 = Vin

    During negative half cycle:

    D1 = ON, D2 = OFF

    Vin < -4 V, V0=(Vin+420k)10k4V

    -4V < Vin < 0 , V0 = Vin (D2 = OFF, D1 = OFF)

    After circuit analysis, the output waveform is as given below.

    (V0)min=((Vin)max+420k)10k4=7V

    Vo min + Vo max = 4 - 7 = -3 V

  • Question 15/25
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    The input voltage (Vin) to the circuit shown in the figure is 2 cos (100t) V. The output voltage (Vout) is 2cos(100tπ2)V. If R = 1 kΩ. The value of C (in μF) is ______

    Solutions

    Given that,

    Vin = 2 cos (100t) V

    Vout=2cos(100tπ2)V.

    R = 1 kΩ = 1000 Ω

    Apply superposition at point A,

    Vin at non-inverted (+) terminal and inverted (-) terminal at the ground.

    V1=Vin(jωC)(RjωC)×(1+RR)

    Now Vin at inverted (-) terminal and non-inverted (+) terminal at the ground.

    V2=Vin(RR)

    So that the output voltage is,

    Vout = V1 + V2

    Vout=Vin(jωC)(RjωC)×(1+RR)Vin(RR)

    Vout=Vin1+jωRC ×(1+11)Vin(11)

    Vout=2×Vin1+jωRCVin  

    Vout=Vin(21jωRC1+jωRC)

    Vout=Vin(1jωRC1+jωRC)

    Vin = 2 cos(100t) and ω = 100rad.

    Vout=2cos(100t2tan1(ωRC))

    2tan1(ωRC)=π2

    ωRC=tanπ4

    ⇒ 100 × 1000 × C = 1

    ⇒ C = 10 μF

  • Question 16/25
    2 / -0.33

    For the circuit shown below, V1 = 10 sin (200 t) and V2 = 15 sin (200 t). What is Vout. Assume the op-amp is ideal with infinite gain.

    Solutions

    By using virtual ground concept,

    Va = Vb = 0 V

    By applying KCL at Va,

    VaV1R1+VaV2R2+VaVout1jωC=0 

    Vout=V2jωCR2V1jωCR1 

    V1 = 10 sin 200 t = 10 cos (200 t – 90°)

    = 10 ∠-90° = -10j

    V2 = 15 sin 200 t = -15 j

    Vout=j15j(200)(2×106)(0.5×106)j10j(200)(2×106)(0.75×106) 

    =15200+10300=0.1083 

    Vout = 0.1083 cos (200 t) 

  • Question 17/25
    2 / -0.33

    The expression for the output voltage of the circuit, shown in the figure is ______

    Solutions

    • The first two op-amps have their inverting inputs at a virtual ground due to the connection to ground at their noninverting inputs.
    • The two 40 kΩ resistor do not induce any voltage drop between the first pair of op-amps, as the currents into the op amp inputs are always 0.
    • Because both of the middle op amps are buffers, Vx and Vy get carried over to their outputs.
    • There is no voltage drop across the bottom 0.5 kΩ resistor due to lock of current.


    Both Vx and Vy are given by inverting amplifiers:

    Vx=8k2kV1=4V1 

    Vy=16k2kV1=8V2 

    KCL at the inverting input of the last op-amp given us

    VyVx0.5k+VyV04k=0 

    V0 = 32 V1 – 72 V2

  • Question 18/25
    2 / -0.33

    In the astable multivibrator circuit shown in the figure, the frequency of oscillation (in kHz) at the output pin is_______

    Solutions

    Concept:

    For a 555 timer, the given pin connection represents an astable 555 timer.

    The charging time is given by the formula.

    ⇒ Tc = 0.693 (R1 + R2) C

    Discharging time ⇒ Td = 0.693 R2 C

    Total time ⇒ T = Tc + Tα = 0.693 (R1 + 2R2)C

    Calculation:

    For the given question

    R1 = 2.2 kΩ; R2 = 4.7 kΩ; C = 0.22 μF

    T = 0.93 (R1 + 2R2)C

    T = 0.693 (2.2 + (2 × 4.7)) × 103 × 0.22 × 10-6

    Frequency of oscillation is

    f=1T=10.693×0.22×11.6×103

    f = 0.565 kHz  

  • Question 19/25
    2 / -0.33

    Find the hysteresis width in the voltage transfer characteristics of the Schmitt trigger circuit given

    Solutions

    Concept:

    Inverting closed-loop positive feedback Schmitt trigger is shown below.

    VUTP=VR1=VsatR1R1+R2

    VLTP=VR2=VsatR1R1+R2

    For Vi < VUTP     V0 = +Vsat

    Vi > VUTP        V0 = -Vsat

    Hysteresis width VH = VUTP - VLTP

    Calculation:

    Vx is the actual inverting input to the op-Amp.

    At node X:

    VxVin10k=2Vx20k

    Vx=2+2Vin3

    VuTP1=VR1=VsatR1R1+R2=10(5k5k+20k)=2V

    For Vx>VuTP1 V0 = -Vsat

    2+3Vin3>2

    i.e. Vin>622=2V

    For Vx > -2V       V0 = +Vsat

    2+2Vin3>2

    VLTP=Vin>622=4V

    VH = VuTP - VLTP = 2 – (-4) = 6 V

  • Question 20/25
    2 / -0.33

    The transistor circuit and its dc load line are shown in figure a and b.

    For the transistor, β = 120. What is the value of emitter resistance (RE) at Q-point (in kΩ)?

    (Correct up to two decimal places)

    Solutions

    From the given dc load line, we have:

    VCEQ = 6 V

    ICQ = 48 mA

    Since, IE = IC + IB

    Since IC = β IB, the emitter current can be written as:

    IE=IC+ICβ

    IE=IC(β+1β)

    For the given ICQ and β, IEQ will be:

    IEQ=4.8m(120+1220)

    IEQ = 4.84 mA

    ∴ The circuit is redrawn as:

    Applying KVL for the above loop, we get:

    18 - ICQ RC - VCEQ - IEQ RE = 0

    18 – 4.8 m × 2x – 6 – 4.84 m × RE = 0

    RE=189.664.84m

    RE = 0.496 kΩ

  • Question 21/25
    2 / -0.33

    In the circuit shown in the figure, the BJT has a current gain (β) of 50. For an emitter-base voltage VEB = 600 mV, the emitter-collector voltage VEC (in Volts) is _____Volts.

    Solutions

    Concept:

    The BJT configuration for a pnp and npn transistors are as shown:

    The emitter-collector voltage can be calculated using KVL

    Analysis:

    The configuration given is of a PNP transistor.

    Given, VE = 3 V

    VEB = 600 × 10-3 V = 0.6 V

    VE – VB ⇒ 0.6 V

    3 – VB ⇒ 0.6 V

    So, VB = 2.4 Volts

    Applying Ohm’s law across 60 kΩ resistor,

    IB=VB60×103=2.460×103

    IB=0.04×103A

    IC = β IB (where β is the current gain)

    Given, β = 50,

    IC = 50 × 0.04 × 10-3 A = 2 mA

    IC = 2 × 10-3 A

    Applying Ohms law across 500 Ω resistor, we get:

    IC=VC500=VC500

    IC=2×103

    VC=1Volts

    Now,

    VEC = V – VC = 3 – 1 = 2 Volts

    So, VEC = 2 Volts

    Common Mistakes:

    Mark emitter & collector terminals accordingly. It is common to notice that students always apply npn-transistor concepts even for a given pnp transistor. 
  • Question 22/25
    2 / -0.33

    In the circuit shown in figure the transistor has β of 200. Find the operating region of transistor.

    Solutions

    β = 200, α = 0.995

    Collector (Ic) = α IE = 0.995 × 10 = 9.95 mA

    Vc = 9.95 × 100 = 0.995 V

    Base current IR=10200=0.05mA

    VB = 1.5 – 10 k × 0.05 = 1 V

    VBC = 0.005

    Transistor working in active region
  • Question 23/25
    2 / -0.33

    For the n-channel enhancement MOSFET shown in figure, the threshold voltage Vth = 2 V. The drain current ID of the MOSFET is 4 mA when the drain resistance RD is 1 kΩ. If the value of RD is increased to 4 kΩ, drain current ID will become

    Solutions

    For an n-channel enhancement mode MOSFET, transition point is given by:

    VDS(sat) = VGS - Vth

    = VGS – 2

    From the circuit,

    VDS = VGS

    ⇒ VDs(sat) = VDS – 2

    ⇒ VDS = VDS(sat) + 2

    ⇒ V­DS > VDS(sat)

    So, the transistor will always be in the Saturation region.

    ID = K (VGS - Vth)2

    ⇒ 4 = K (VGS - 2)2

    VGS = VDS = 10 – ID R­D = 10 – 4(1) = 6 V

    ⇒ 4 = K (6 -2)2

    ⇒ K = 0.25

    Now RD is increased to 4 kΩ, Let current Id and voltages are VDS=VGS

    Applying current equation

    ID=K(VGSVTH)2

    ID=14(VGS2)2

    VGS=VDS=10IDRD=104ID

    4IDS=(104ID2)2=(84ID)2

    =16(2ID)2

    ID=4(4+ID4ID)

    4(ID)217ID+16=0

    ID=2.84mA or 1.4 mA

    It cannot be 2.84 mA because:

    For ID = 2.84 mA, VGS will be negative.

    So, ID' = 1.4 mA

  • Question 24/25
    2 / -0.33

    In the circuit shown V0 = 12 V, |VGS|=2V the value of R

    Solutions

    In Thevenin’s equivalent circuit

    Vth=20(50K50K+R)

    VGS = Vth - 6K ID

    ID=20123K=2.67mA

    For PMOS CKT VGS should be -Ve

    VGS = -2V

    2=20(50KR+50K)5×2.6711.35=20(50K50K+R)50K0.567=50K+R

    88.105 K = 50 K + R

    R = 38.11 KΩ
  • Question 25/25
    2 / -0.33

    The parameter of the transistor shown below are VTN=1.2mAV2,Kn=0.5mAV2,λ=0 the voltage VDS is__ (in V)

    Solutions
    Is=50mA=IDID=Kn(VGSVTN)250×106=0.5×103(VGS1.2)2VGS=1.516VVG=0,Vs=VGVGS=1.516VVDS=VDVS=5(1.516)=6.516V
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